Datasheet

TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
double-buffered mode (MODE = 0)
In this mode, data is only latched to the output of the DACs on the falling edge of the EN strobe. Therefore, all
four DACs can be written to before updating their outputs.
Any number of input data blocks can be written with all having the same length. Subsequent data blocks simply
overwrite previous ones with the same address until EN goes low.
Multiple data blocks can be written in any sequence provided signal timing limits are met. The negative going
edge of EN terminates and latches all data.
Data Latched Into DAC Control Registers and Control Word
Multiple Random Sequence Data Blocks
DATA
EN
Figure 3. Data and Control Serial Control