Datasheet

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
T
emp
l
ate
R
e
l
ease
D
ate:
7
–
11
–
94
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
CLK
RS
MODE
RNG
A
RNG
B
RNG
C
RNG
D
SIA SIB SIC SID ACT
DATA
DAC
EN
(Tied High)
NOTE A: Twelve zeros enable word synchronization and the output can change after the leading edge of CLK depending on the data in the latches.
Figure 1. Register Write Operation Following Noise or Undefined Levels on DATA or CLK (Single-Buffer Mode)
CLK
RS
MODE
RNG
A
RNG
B
RNG
C
RNG
D
SIA SIB SIC SID ACTDATA
DAC
EN
(Tied High)
NOTE A: EN is held high and data is written to a DAC register. The data is latched to the output of the DAC on the falling edge of the last CLK of the control word, where the
mode is set.
RS A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 2. First Nonzero Write Operation After Startup (EN = High)