Datasheet

TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Power-On
Reset
Serial
Interface
× 2
DAC
LatchLatch
Latch Latch
DAC
× 2
× 2
DAC
LatchLatch
Latch Latch
DAC
× 2
REFA
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
REFB
REFC
CLK
REFD
DATA
EN
DACA
DACB
DACC
DACD
8 8
8
8
8
8
8
8
HWACT
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
CLK 7 I Serial interface clock, data enters on the negative edge
DACA 12 O DAC A analog output
DACB 11 O DAC B analog output
DACC 10 O DAC C analog output
DACD 9 O DAC D analog output
DATA 6 I Serial-interface digital-data input
EN 8 I Input enable
GND 1 Ground return and reference
HWACT 13 I Global hardware activate
REFA 2 I Reference voltage input to DACA
REFB 3 I Reference voltage input to DACB
REFC 4 I Reference voltage input to DACC
REFD 5 I Reference voltage input to DACD
V
DD
14 Positive supply voltage
detailed description
The TLV5621 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected
to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use
of the resistor strings. Linearity depends upon the matching of the resistor elements and upon the performance
of the output buffer. Because the inputs are buffered, the DACs always present a high-impedance load to the
reference source.