Datasheet

TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
POSITIVE RISE TIME AND SETTLING TIME
V
DD
= 3 V
T
A
= 25°C
Code 00 to
FF Hex
Range = ×2
V
ref
= 1.25 V
(see Notes
A and B)
t – Time – µs
024681012
– Output Voltage – V
14 16 18 20
–1
–0.5
0.5
1
1.5
2
2.5
0
3
V
O
NOTES: A. Rise time = 2.05 µs, positive slew rate = 0.96 V/µs,
settling time = 4.5 µs.
B. For DACB, DACC, and DACD
Figure 10
NEGATIVE FALL TIME AND SETTLING TIME
V
DD
= 3 V
T
A
= 25°C
Code FF to
00 Hex
Range = ×2
V
ref
= 1.25 V
(see Notes
A and B)
t – Time – µs
024681012
– Output Voltage – V
14 16 18 20
–1
–0.5
0.5
1
1.5
2
2.5
0
3
V
O
NOTES: A. Fall time = 4.25 µs, negative slew rate = 0.46 V/µs,
settling time = 8.5 µs.
B. For DACB, DACC, and DACD
Figure 11
2
1.8
1.4
1.2
1
2.8
1.6
0 102030405060
– DAC Output Voltage – V
2.4
2.2
2.6
DAC OUTPUT VOLTAGE
vs
LOAD RESISTANCE
3
70 80 90 100
V
O
R
L
– Load Resistance – kΩ
V
DD
= 3 V
V
ref
= 1.5 V
Range = ×2
(see Note A)
NOTE A: For DACB, DACC, and DACD
Figure 12
0.8
0.6
0.2
0
0102030405060
1
1.4
1.6
70 80 90 100
0.4
1.2
DAC OUTPUT VOLTAGE
vs
LOAD RESISTANCE
V
DD
= 3 V
V
ref
= 1.5 V
Range = ×1
(see Note A)
– DAC Output Voltage – V
V
O
R
L
– Load Resistance – kΩ
NOTE A: For DACB, DACC, and DACD