Datasheet

TLV5618A
2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT
DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS230H – JULY 1999 – REVISED JULY 2002
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
digital input timing requirements
MIN NOM MAX UNIT
C and I suffixes
V
DD
= 5 V 5
ns
t
su
(
CS-CK
)
Setup time, CS low before first negative SCLK edge
C and I suffixes
V
DD
= 3 V 10
ns
t
su(CS
-
CK)
Setu
time,
CS
low
before
first
negative
SCLK
edge
Q and M suffixes 10 ns
t
su(C16-CS)
Setup time, 16
th
negative SCLK edge before CS rising edge 10 ns
t
w(H)
SCLK pulse width high 25 ns
t
w(L)
SCLK pulse width low 25 ns
C and I suffixes
V
DD
= 5 V 5
t
su
(
D
)
Setup time, data ready before SCLK falling edge
C and I suffixes
V
DD
= 3 V 10
ns
t
su(D)
Setu
time,
data
ready
before
SCLK
falling
edge
Q and M suffixes 8
ns
C and I suffixes
V
DD
= 5 V 5
t
h(D)
Hold time, data held valid after SCLK falling edge
C and I suffixes
V
DD
= 3 V 10
ns
h(D)
gg
Q and M suffixes 10
t
h(CSH)
Hold time CS high between cycles
V
DD
= 5 V
25
ns
t
h(CSH)
Hold time, CS high between cycles
V
DD
= 3 V
50
ns
timing requirements
t
w(L)
SCLK
CS
DIN
D15 D14 D13 D12 D1 D0 XX
1
X
2 3 4 5 15 16
X
t
w(H)
t
su(D)
t
h(D)
t
su(CS-CK)
t
su(C16-CS)
Figure 1. Timing Diagram