Datasheet

TLV5617A
2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS234F – JULY 1999 – REVISED JULY 2002
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
digital input timing requirements
MIN NOM MAX UNIT
t
Setup time CS low before first negative SCLK edge
V
DD
= 2.7 V to 3.3 V 10
ns
t
su(CS–CK)
Setup time, CS low before first negative SCLK edge
V
DD
= 4.5 V to 5.5 V
5
ns
t
su(C16-CS)
Setup time, 16
th
negative SCLK edge before CS rising edge 10 ns
t
wH
SCLK pulse width high 25 ns
t
wL
SCLK pulse width low 25 ns
t
Setup time data ready before SCLK falling edge
V
DD
= 2.7 V to 3.3 V 10
ns
t
su(D)
Setup time, data ready before SCLK falling edge
V
DD
= 4.5 V to 5.5 V
5
ns
t
h(D)
Hold time data held valid after SCLK falling edge
V
DD
= 2.7 V to 3.3 V 10
ns
t
h(D)
Hold time, data held valid after SCLK falling edge
V
DD
= 4.5 V to 5.5 V 5
ns
timing requirements
t
wL
SCLK
CS
DIN
D15 D14 D13 D12 D1 D0 XX
1
X
234 1516
X
t
wH
t
su(D)
t
h(D)
t
su(CS-CK)
t
su(C16-CS)
Figure 1. Timing Diagram