Datasheet

TLV5617A
2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS234F – JULY 1999 – REVISED JULY 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)
digital inputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
IH
High-level digital input current V
I
= V
DD
1 µA
I
IL
Low-level digital input current V
I
= 0 V –1 µA
C
i
Input capacitance 8 pF
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
Output settling time full scale
R10kΩ C 100 pF See Note 11
Fast 1 3
s
t
s(FS)
Output settling time, full scale R
L
= 10 kΩ,C
L
= 100 pF, See Note 11
Slow 3 10
µs
t
Output settling time code to code
R10kΩ C 100 pF See Note 12
Fast 1
s
t
s(CC)
Output settling time, code to code R
L
= 10 kΩ,C
L
= 100 pF, See Note 12
Slow 2
µs
SR
Slew rate
R10kΩ C 100 pF See Note 13
Fast 3
V/ s
SR Slew rate R
L
= 10 kΩ,C
L
= 100 pF, See Note 13
Slow 0.5
V/µs
Glitch energy DIN = 0 to 1, FCLK = 100 kHz, CS = V
DD
5 nV–s
SNR Signal-to-noise ratio 68
SINAD Signal-to-noise + distortion
f
s
= 102 kSPS, f
out
= 1 kHz, R
L
= 10 kΩ,
65
dB
THD Total harmonic distortion
f
s
=
102
kSPS
,
f
out
=
1
kHz
,
R
L
=
10
kΩ
,
C
L
= 100 pF
–62
dB
SFDR Spurious free dynamic range
L
64
NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFDC and 0xFDC to 0x020 respectively. Not tested, assured by design.
12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.