Datasheet

TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR
Output slew rate
C
L
= 100 pF, R
L
= 10 kΩ,
V
O
10% to 90%
Fast 5 V/µs
SR Output slew rate
V
O
= 10% to 90%,
V
ref
= 2.048 V, 1024 V
Slow 1 V/µs
t
Output settling time
To ± 0.5 LSB, C
L
= 100 pF,
Fast 3 5.5
s
t
s
Output settling time
To
± 0
.
5
LSB
,
C
L
=
100
F
,
R
L
= 10 kΩ, See Notes 12 and 14
Slow 9 20
µs
t
Output settling time code to code
To ± 0.5 LSB, C
L
= 100 pF,
Fast 1
s
t
s(c)
Output settling time, code to code
To
± 0
.
5
LSB
,
C
L
=
100
F
,
R
L
= 10 kΩ, See Note 13
Slow 2
µs
Glitch energy Code transition from 7FF to 800 10 nV-sec
SNR Signal-to-noise ratio
Sinewave generated by DAC,
R f lt 1 024 t 3 V d 2 048 t 5 V
74
S/(N+D) Signal to noise + distortion
Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
f
s
= 400 KSPS
,
66
dB
THD Total harmonic distortion
f
s
=
400
KSPS
,
f
OUT
= 1.1 kHz sinewave,
C
L
= 100
p
FR
L
=10kΩ
–68
dB
SFDR Spurious free dynamic range
C
L
= 100 pF, R
L
= 10 kΩ,
BW = 20 kHz
70
NOTES: 12. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
ofFFF hex to 080 hex for 080 hex to FFF hex.
13. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of one count.
14. Limits are ensured by design and characterization, but are not production tested.