Datasheet

TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614 interfaced to TMS320C203 DSP
hardware interfacing
Figure 17 shows an example of how to connect the TLV5614 to a TMS320C203 DSP. The serial port is
configured in burst mode, with FSX generated by the TMS320C203 to provide the frame sync (FS) input to the
TLV5614. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The general-purpose
input/output port bits IO0 and IO1 are used to generate the chip select (CS
) and DAC latch update (LDAC) inputs
to the TLV5614. The active low power down (PD
) is pulled high all the time to ensure the DACs are enabled.
DX
CLKX
FSX
I/O 0
I/O 1
TMS320C203
SDIN
SCLK
FS
CS
LDAC
REF
V
DD
PD
VOUTA
VOUTB
VOUTC
VOUTD
V
SS
TLV5614
REFINAB
REFINCD
Figure 18. TLV5614 Interfaced With TMS320C203
software
The application example outputs a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and
its quadrature (cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses
LDAC
low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The
samples are stored in a look-up table, which describes two full periods of a sine wave.
The synchronous serial port of the DSP is used in burst mode. In this mode, the processor generates an FS
pulse preceding the MSB of every data word. If multiple, contiguous words are transmitted, a violation of the
tsu(C16–FS) timing requirement occurs. To avoid this, the program waits until the transmission of the previous
word has been completed.