Datasheet
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR
Out
p
ut slew rate
C
L
= 100 pF, R
L
= 10 kΩ,
V
O
10% to 90%
Fast 5 V/µs
SR
Output
slew
rate
V
O
=
10%
t
o
90%
,
V
ref
= 2.048 V, 1024 V
Slow 1 V/µs
t
Out
p
ut settling time
To ± 0.5 LSB, C
L
= 100 pF,
Fast 2.5 4
µs
t
s
Output
settling
time
,
L
,
R
L
= 10 kΩ, See Notes 12 and 14
Slow 8.5 18
µ
s
t
()
Out
p
ut settling time code to code
To ± 0.5 LSB, C
L
= 100 pF,
Fast 1
µs
t
s(c)
Output
settling
time
,
code
to
code
,
L
,
R
L
= 10 kΩ, See Note 13
Slow 2
µ
s
Glitch energy Code transition from 7FF to 800 10 nV-sec
SNR Signal-to-noise ratio
Sinewave generated by DAC,
R f l 1 024 3 V d 2 048 5 V
68
S/(N+D) Signal to noise + distortion
Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
f
s
= 4
00
K
S
P
S,
65
dB
THD Total harmonic Distortion
f
s
=
400
KSPS
,
f
OUT
= 1.1 kHz sinewave,
C
L
= 100
p
FR
L
=10kΩ
–68
dB
SFDR Spurious free dynamic range
C
L
=
100
pF
,
R
L
=
10
kΩ
,
BW = 20 kHz
70
NOTES: 12. Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
13. Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change
of one count, 1FF hex to 200 hex.
14. Limits are ensured by design and characterization, but are not production tested.