Datasheet

TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
individual DAC output specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
O
Voltage output R
L
= 10 kΩ 0 AV
DD
–0.4 V
Output load regulation accuracy R
L
= 2 kΩ vs 10 kΩ 0.1 0.25
% of FS
voltage
reference input (REFINAB, REFINCD)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
I
Input voltage range See Note 10 0 AV
DD
–1.5 V
R
I
Input resistance 10 MΩ
C
I
Input capacitance 5 pF
Reference feed through
REFIN = 1 V
pp
at 1 kHz + 1.024 V dc
(see Note 11)
–75 dB
Reference in
p
ut bandwidth
REFIN = 0 2 V + 1 024 V dc
Slow 0.5
MHz
Reference
input
bandwidth
REFIN
=
0
.
2
V
pp
+
1
.
024
V
dc
Fast 1
MHz
NOTES: 10. Reference input voltages greater than V
DD
/2 will cause output saturation for large DAC codes.
11. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V
ref(REFINAB or REFINCD)
input = 1.024 Vdc + 1 V
pp
at 1 kHz.
digital inputs (D0–D11, CS, WEB, LDAC, PD)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
IH
High-level digital input current V
I
= DV
DD
±1 µA
I
IL
Low-level digital input current V
I
= 0 V ±1 µA
C
I
Input capacitance 3 pF
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
5Vsu
pp
ly No load Clock running
Slow 1.4 2.2
mA
I
DD
Power su
pp
ly current
5
-
V
supply
,
No
load
,
Clock
running
Fast 3.5 5.5
mA
I
DD
Power
supply
current
3Vsu
pp
ly No load Clock running
Slow 1 1.5
mA
3
-
V
supply
,
No
load
,
Clock
running
Fast 3 4.5
mA
Power down supply current,
See Figure 12
10 nA