Datasheet

TLV320DAC32
SLAS506B NOVEMBER 2006 REVISED DECEMBER 2008 ........................................................................................................................................
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Page 0 / Register 11: Audio DAC Overflow Flag Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 D6 R 0 Reserved. Only write zeroes to these bits.
D5 R 0 Left DAC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D4 R 0 Right DAC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D3 D0 R/W 0001 PLL R Value
0000: R = 16
0001 : R = 1
0010 : R = 2
0011 : R = 3
0100 : R = 4
1110: R = 14
1111: R = 15
Page 0 / Register 12: Audio DAC Digital Filter Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 D4 R/W 00 Reserved. Only write zeroes to these bits.
D3 R/W 0 Left DAC Digital Effects Filter Control
0: Left DAC digital effects filter disabled (bypassed)
1: Left DAC digital effects filter enabled
D2 R/W 0 Left DAC De-emphasis Filter Control
0: Left DAC de-emphasis filter disabled (bypassed)
1: Left DAC de-emphasis filter enabled
D1 R/W 0 Right DAC Digital Effects Filter Control
0: Right DAC digital effects filter disabled (bypassed)
1: Right DAC digital effects filter enabled
D0 R/W 0 Right DAC De-emphasis Filter Control
0: Right DAC de-emphasis filter disabled (bypassed)
1: Right DAC de-emphasis filter enabled
Page 0 / Register 13: Headset / Button Press Detection Register A
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 Headset Detection Control
0: Headset detection disabled
1: Headset detection enabled
D6-D5 R 00 Headset Type Detection Results
00: No headset detected
01: Stereo headset detected
10: Cellular headset detected
11: Stereo + cellular headset detected
D4-D2 R/W 000 Headset Glitch Suppression Debounce Control for Jack Detection
000: Debounce = 16msec( sampled with 2ms clock)
001: Debounce = 32msec( sampled with 4ms clock)
010: Debounce = 64msec( sampled with 8ms clock)
011: Debounce = 128msec( sampled with 16ms clock)
100: Debounce = 256msec( sampled with 32ms clock)
101: Debounce = 512msec( sampled with 64ms clock)
110: Reserved, do not write this bit sequence to these register bits.
111: Reserved, do not write this bit sequence to these register bits.
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