Datasheet
TLV320DAC32
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........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008
Page 0 / Register 10: Audio Serial Data Interface Control Register C
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 00000000 Audio Serial Data Word Offset Control
This register determines where valid data is placed or expected in each frame, by controlling
the offset from beginning of the frame where valid data begins. The offset is measured from
the rising edge of word clock when in DSP mode.
00000000: Data offset = 0 bit clocks
00000001: Data offset = 1 bit clock
00000010: Data offset = 2 bit clocks
…
Note: In continuous transfer mode the maximum offset is 17 for I
2
S/LJF/RJF modes and 16
for DSP mode. In 256-clock mode, the maximum offset is 242 for I
2
S/LJF/RJF and 241 for
DSP modes.
11111110: Data offset = 254 bit clocks
11111111: Data offset = 255 bit clocks
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