Datasheet

TLV320DAC32
A
HPLOUT
PWR
AMP
HPLCOM
PWR
AMP
HPRCOM
PWR
AMP
HPROUT
PWR
AMP
LINER
ToDetection
Block
SW1
DifferentialHeadphone
Connector Assembly
CONTROL REGISTERS
TLV320DAC32
www.ti.com ........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008
Figure 37. Configuration of device for jack detection using a fully differential stereo headphone output
connection.
The control registers for the TLV320DAC32 are described in detail below. All registers are 8-bit in width, with D7
referring to the most significant bit of each register, and D0 referring to the least significant bit.
Page 0 / Register 0: Page Select Register
BIT
(1)
READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D1 X 0000000 Reserved, write only zeros to these register bits
D0 R/W 0 Page Select Bit
Writing zero to this bit sets Page-0 as the active page for following register accesses. Writing a
one to this bit sets Page-1 as the active page for following register accesses. It is recommended
that the user read this register bit back after each write, to ensure that the proper page is being
accessed for future register read/writes.
(1) When resetting registers related to routing and volume controls of output drivers, it is recommended to reset them by writing directly to
the registers instead of using software reset.
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