Datasheet

n-1 n-2 n-3 n-1 n-2 n-3
I
2
S MODE
n-1 n-2 n-3 n-1 n-2 n-3
DSP MODE
BCLK
WCLK
SDIN
n−2 n−3 1 0 n−1 n−2 1 0
1/fs
LSBMSB
LeftChannel RightChannel
n−1
MSB LSB
n−4 2 n−3 2
MSBLSB
TLV320DAC32
SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com
Figure 27. Left Justified Serial Data Bus Mode Operation
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock.
Figure 28. I
2
S Serial Data Bus Mode Operation
In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and
immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.
Figure 29. DSP Serial Bus Mode Operation
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