Datasheet
LDO=OFF
TLV320DAC32
IOVDD
D
IOVDD
3.3V
1 Fm
0.1 Fm
DVDD
IOVSS
LDO_SELECT
DVDD
1.8V
1 Fm
0.1 Fm
HARDWARE RESET
FLEXIBLE POWER DOWN
DIGITAL CONTROL SERIAL INTERFACE
TLV320DAC32
SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 ........................................................................................................................................
www.ti.com
A. See tables for voltage range of DVDD and IOVDD
Figure 22. LDO Function Bypassed, DVDD Supplied Externally
The TLV320DAC32 requires a hardware reset after power-up for proper operation. After all power supplies are at
their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the 'DAC32 may not respond properly to register reads/writes.
The TLV320DAC32 allows power down for many individual circuit blocks. This flexibility allows the user to be
able to optimize functionality while minimizing power consumption for each application. The power consumption
for the device by function can be seen in Table 1 .
Table 1. Total Power Dissipation
FUNCTION POWER DISSIPATION UNITS
Headphone amplifier only 13.2 mW
DAC + headphone amplifier, 18.1 mW
(Analog Mixer bypassed) PLL
= off, LDO = off
DAC + headphone amplifier, 20.2 mW
PLL = off, LDO = off
DAC + headphone amplifier, 25.2 mW
PLL = on, LDO = off
Power down 1.23 µ W
The register map of the TLV320DAC32 actually consists of two pages of registers, with each page containing
128 registers. The register at address zero on each page is used as a page control register, and writing to this
register determines the active page for the device. All subsequent read/write operations will access the page that
is active at the time, unless a register write is performed to change the active page. Only two pages of registers
are implemented in this product, with the active page defaulting to page 0 upon device reset. The Page 0 is
dedicated to DAC and device functionality setup, while Page 1 is used to setup the Digital Audio Effects
Processor, and for use in applying digital de-emphasis to the digital audio playback stream.
For example, at device reset, the active page defaults to page 0, and thus all register read/write operations for
addresses 1 to 127 will access registers in page 0. If registers on page 1 must be accessed, the user must write
the 8-bit sequence “ 0x01 ” to register 0, the page control register, to change the active page from page 0 to page
1. After this write, it is recommended the user also read back the page control register, to safely ensure the
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