Datasheet

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6.6.1 Use Without PLL
6.6.2 Use With The PLL
Kit Operation
Figure 3. Clocks Tab
The codec clock source is chosen by the DAC_CLK Source control. When this control is set to
CLKDIV_OUT, the PLL is not used; when set to PLLDIV_OUT, the PLL is used to generate the clocks.
Setting up the TLV320DAC32 for clocking without using the PLL is straightforward. The CLKDIV_IN
source can be selected as either MCLK or BCLK, the default is MCLK. The CLKDIV_IN frequency is then
entered into the CLKDIV_IN box, in megahertz (MHz). The default value shown, 11.2896MHz, is the
frequency used on the USB-MODEVM board. This value is then divided by the value of Q, which can be
set from 2 to 17; the resulting CLKDIV_OUT frequency is shown in the indicator next to the Q control.
This frequency will then be used to calculate the actual Fsref frequency, and the DAC sample rate, after
the NADC factor is applied to the Fsref. If dual rate mode is desired, this option can be enabled for the
DAC by pressing the corresponding Dual Rate Mode button.
When PLLDIV_OUT is selected as the codec clock source, the PLL will be used. The PLL clock source is
chosen using the PLLCLK_IN control, and may be set to either MCLK or BCLK. The PLLCLK_IN
frequency is then entered into the PLLCLK_IN Source box.
The PLL_OUT and PLLDIV_OUT indicators show the resulting PLL output frequencies with the values set
for the P, K, and R parameters of the PLL. See the TLV320DAC32 data sheet for an explanation of these
parameters. The parameters can be set by clicking on the up/down arrows of the P, K, and R combo
boxes, or they can be typed into these boxes. The values can also be calculated by the PC software.
12 TLV320DAC32EVM and TLV320DAC32EVM-PDK SLAU201 – November 2006
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