Datasheet

TLV320DAC3101
www.ti.com SLAS666A –JANUARY 2010–REVISED MAY 2012
Page 1 / Register 47 (0x2F) Through Page 1 / Register 49 (0x31): Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R XXXX XXXX Reserved. Do not write to these bits.
Page 1 / Register 50 (0x32): Input CM Settings
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: AIN1 input is floating if it is not used for analog bypass.
1: AIN1 input is connected to CM internally if it is not used for analog bypass.
D6 R/W 0 0: AIN2 input is floating if it is not used for analog bypass.
1: AIN2 input is connected to CM internally if it is not used for analog bypass.
D5–D0 R/W 000000 Reserved. Write only zeros to these bits.
Page 1 / Register 51 (0x33) Through Page 1 / Register 127 (0x7F): Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W XXXX XXXX Reserved. Write only the reset value to these bits.
6.4 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
Default values shown for this page only become valid 100 μs following a hardware or software reset.
Page 3 / Register 0 (0x00): Page Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
The only register used in page 3 is register 16. The remaining page-3 registers are reserved and should
not be written to.
Page 3 / Register 16 (0x10): Timer Clock MCLK Divider
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 1 0: Internal oscillator is used for programmable delay timer.
1: External MCLK
(1)
is used for programmable delay timer.
D6–D0 R/W 0000 0001 MCLK Divider to Generate 1-MHz Clock for the Programmable Delay Timer
000 0000: MCLK divider = 128
000 0001: MCLK divider = 1
000 0010: MCLK divider = 2
...
111 1110: MCLK divider = 126
111 1111: MCLK divider = 127
(1) External clock is used only to control the delay programmed between the conversions and not used for doing the actual conversion. This
feature is provided in case a more accurate delay is desired, because the internal oscillator frequency varies from device to device.
6.5 Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63)
Default values shown for this page only become valid 100 μs following a hardware or software reset.
Page 8 / Register 0 (0x00): Page Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
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