Datasheet
TLV320DAC3101
www.ti.com
SLAS666A –JANUARY 2010–REVISED MAY 2012
Page 0 / Register 33 (0x21): Codec Secondary Interface Control 3
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: Primary BCLK output = internally generated BCLK clock
1: Primary BCLK output = secondary BCLK
D6 R/W 0 0: Secondary BCLK output = primary BCLK
1: Secondary BCLK output = internally generated BCLK clock
D5–D4 R/W 00 00: Primary WCLK output = internally generated DAC_f
S
01: Reserved
10: Primary WCLK output = secondary WCLK
11: Reserved
D3–D2 R/W 00 00: Secondary WCLK output = primary WCLK
01: Secondary WCLK output = internally generated DAC_f
S
clock
10: Reserved
11: Reserved
D1–D0 R/W 00 Reserved
Page 0 / Register 34 (0x22): I
2
C Bus Condition
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D6 R/W 00 Reserved. Write only the reset value to these bits.
D5 R/W 0 0: I
2
C general-call address is ignored.
1: Device accepts I
2
C general-call address.
D4–D0 R/W 0 0000 Reserved. Write only zeros to these bits.
Page 0 / Register 35 (0x23) and Page 0 / Register 36 (0x24): Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W XXXX XXXX Reserved. Write only zeros to these bits.
Page 0 / Register 37 (0x25): DAC Flag Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R 0 0: Left-channel DAC powered down
1: Left-channel DAC powered up
D6 R/W X Reserved. Write only zero to this bit.
D5 R 0 0: HPL driver powered down
1: HPL driver powered up
D4 R 0 0: Left-channel class-D driver powered down
1: Left-channel class-D driver powered up
D3 R 0 0: Right-channel DAC powered down
1: Right-channel DAC powered up
D2 R/W X Reserved. Write only zero to this bit.
D1 R 0 0: HPR driver powered down
1: HPR driver powered up
D0 R 0 0: Right-channel class-D driver powered down
1: Right-channel class-D driver powered up
Page 0 / Register 38 (0x26): DAC Flag Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D5 R/W XXX Reserved. Do not write to these bits.
D4 R 0 0: Left-channel DAC PGA applied gain ≠ programmed gain
1: Left-channel DAC PGA applied gain = programmed gain
D3–D1 R/W XXX Reserved. Write only zeros to these bits.
D0 R 0 0: Right-channel DAC PGA applied gain ≠ programmed gain
1: Right-channel DAC PGA applied gain = programmed gain
Copyright © 2010–2012, Texas Instruments Incorporated REGISTER MAP 69
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