Datasheet

TLV320DAC3100
SLAS671A –FEBRUARY 2010–REVISED MAY 2012 www.ti.com
Page 0 / Register 46 (0x2E): DAC Interrupt Flags
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R 0 0: No short circuit detected at HPL/left class-D driver
1: Short circuit detected at HPL/left class-D driver
D6 R 0 0: No short circuit detected at HPR/right class-D driver
1: Short circuit detected at HPR/right class-D driver
D5 R X 0: No headset button pressed
1: Headset button pressed
D4 R X 0: Headset removal detected
1: Headset insertion detected
D3 R 0 0: Left DAC signal power is ≤ the signal threshold of the DRC.
1: Left DAC signal power is > the signal threshold of the DRC.
D2 R 0 0: Right DAC signal power is ≤ the signal threshold of the DRC.
1: Right DAC signal power is > the signal threshold of the DRC.
D1–D0 R 00 Reserved
Page 0 / Register 47 (0x2F): Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 Reserved. Write only the reset value to these bits.
Page 0 / Register 48 (0x30): INT1 Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: Headset-insertion detect interrupt is not used in the generation of INT1 interrupt.
1: Headset-insertion detect interrupt is used in the generation of INT1 interrupt.
D6 R/W 0 0: Button-press detect interrupt is not used in the generation of INT1 interrupt.
1: Button-press detect interrupt is used in the generation of INT1 interrupt.
D5 R/W 0 0: DAC DRC signal-power interrupt is not used in the generation of INT1 interrupt.
1: DAC DRC signal-power interrupt is used in the generation of INT1 interrupt.
D4 R/W 0 Reserved
D3 R/W 0 0: Short-circuit interrupt is not used in the generation of INT1 interrupt.
1: Short-circuit interrupt is used in the generation of INT1 interrupt.
D2 R/W 0 0: DAC data overflow does not result in an INT1 interrupt.
1: DAC data overflow results in an INT1 interrupt.
D1 R/W 0 Reserved
D0 R/W 0 0: INT1 is only one pulse (active-high) of typical 2-ms duration.
1: INT1 is multiple pulses (active-high) of typical 2-ms duration and 4-ms period, until page 0 /
register 44 is read by the user.
Page 0 / Register 49 (0x31): INT2 Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: Headset-insertion detect interrupt is not used in the generation of INT2 interrupt.
1: Headset-insertion detect interrupt is used in the generation of INT2 interrupt.
D6 R/W 0 0: Button-press detect interrupt is not used in the generation of INT2 interrupt.
1: Button-press detect interrupt is used in the generation of INT2 interrupt.
D5 R/W 0 0: DAC DRC signal-power interrupt is not used in the generation of INT2 interrupt.
1: DAC DRC signal-power interrupt is used in the generation of INT2 interrupt.
D4 R/W 0 Reserved
D3 R/W 0 0: Short-circuit interrupt is not used in the generation of INT2 interrupt.
1: Short-circuit interrupt is used in the generation of INT2 interrupt.
D2 R/W 0 0: DAC data overflow does not result in an INT2 interrupt.
1: DAC data overflow results in an INT2 interrupt.
D1 R/W 0 Reserved
D0 R/W 0 0: INT2 is only one pulse (active-high) of typical 2-ms duration.
1: INT2 is multiple pulses (active-high) of typical 2-ms duration and 4-ms period, until page 0 /
register 44 is read by the user.
68 REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated
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