Datasheet

TLV320DAC3100
www.ti.com SLAS671A –FEBRUARY 2010–REVISED MAY 2012
Page 0 / Register 39 (0x27): Overflow Flags
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7
(1)
R 0 Left-Channel DAC Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D6
(1)
R 0 Right-Channel DAC Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D5
(1)
R 0 DAC Barrel Shifter Output Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D4–D0 R 0 0000 Reserved
(1) Sticky flag bits. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs
again.
Page 0 / Register 40 (0x28) Through Page 0 / Register 43 (0x2B): Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R XXXX XXXX Reserved. Do not use.
Page 0 / Register 44 (0x2C): DAC Interrupt Flags (Sticky Bits)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7
(1)
R 0 0: No short circuit is detected at HPL/left class-D driver.
1: Short circuit is detected at HPL/left class-D driver.
D6
(1)
R 0 0: No short circuit is detected at HPR/right class-D driver.
1: Short circuit is detected at HPR/right class-D driver.
D5
(1)
R X 0: No headset button pressed
1: Headset button pressed
D4
(1)
R X 0: No headset insertion/removal is detected.
1: Headset insertion/removal is detected.
D3
(1)
R 0 0: Left DAC signal power is ≤ the signal threshold of DRC.
1: Left DAC signal power is > the signal threshold of DRC.
D2
(1)
R 0 0: Right DAC signal power is ≤ the signal threshold of DRC.
1: Right DAC signal power is > the signal threshold of DRC.
D1–D0 R 00 Reserved
(1) Sticky flag bits. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs
again.
Page 0 / Register 45 (0x2D): Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R 0000 0000 Reserved. Do not use.
Copyright © 2010–2012, Texas Instruments Incorporated REGISTER MAP 67
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