Datasheet

BCLK_OUT
DAC_f
S
Clock
Generation
BCLK
S_BCLK
WCLK
S_WCLK
DIN
S_DIN
Audio
Digital
Serial
Interface
BCLK_INT
DAC_WCLK_INT
DIN_INT
BCLK
WCLK
BCLK
DIN
WCLK
DIN
DOUT
Primary
Audio
Processor
S_WCLK
S_BCLK
BCLK_OUT
GPIO1
GPIO1
S_BCLK
BCLK
BCLK_OUT
S_WCLK
WCLK
DAC_f
S
DAC_f
S
GPIO1
S_DIN
WCLK
DIN
DOUT
Secondary
Audio
Processor
BCLK
BCLK2
WCLK2
B0375-01
TLV320DAC3100
SLAS671A –FEBRUARY 2010–REVISED MAY 2012 www.ti.com
Figure 5-34. Audio Serial Interface Multiplexing
5.7.3 Control Interface
The TLV320DAC3100 control interface supports the I
2
C communication protocol.
5.7.3.1 I
2
C Control Mode
The TLV320DAC3100 supports the I
2
C control protocol and responds to the I
2
C address of 0011 000. I
2
C
is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on
the I
2
C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines
HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no
device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus
simultaneously, there is no driver contention.
58 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320DAC3100