Datasheet

TLV320DAC3100
www.ti.com SLAS671A –FEBRUARY 2010–REVISED MAY 2012
Table 5-29. Primary and Secondary Audio Interface Selection (continued)
Desired Pin Possible
Page 0 Registers Comment
Function Pins
Primary WCLK (IN) WCLK R27/D2 = 0 Primary WCLK is input to codec
R27/D3 = 1 Primary BCLK is output from codec
Primary BCLK
BCLK
(OUT)
R33/D7 Select source of primary WCLK (internal BCLK or secondary BCLK)
Primary BCLK (IN) BCLK R27/D3 = 0 Primary BCLK is input to codec
Primary DIN (IN) DIN R32/D0 Select DIN to internal interface (0 = primary DIN; 1 = secondary DIN)
R31/D4–D2 = 000 Secondary WCLK obtained from GPIO1 pin
Secondary WCLK
GPIO1 R51/D5–D2 = 1001 GPIO1 = secondary WCLK output
(OUT)
R33/D3–D2 Select source of secondary WCLK (DAC_fs, or primary WCLK)
R31/D4–D2 = 000 Secondary WCLK obtained from GPIO1 pin
Secondary WCLK
GPIO1
(IN)
R51/D5–D2 = 0001 GPIO1 enabled as secondary input
R31/D7–D5 = 000 Secondary BCLK obtained from GPIO1 pin
Secondary BCLK
GPIO1 R51/D5–D2 = 1000 GPIO1 = secondary BCLK output
(OUT)
R33/D6 Select source of secondary BCLK (primary BCLK or internal BCLK)
R31/D7–D5 = 000 Secondary BCLK obtained from GPIO1 pin
Secondary BCLK
GPIO1
(IN)
R51/D5–D2 = 0001 GPIO1 enabled as secondary input
R31/D1–D0 = 00 Secondary DIN obtained from GPIO1 pin
Secondary DIN (IN) GPIO1
R51/D5–D2 = 0001 GPIO1 enabled as secondary input
Copyright © 2010–2012, Texas Instruments Incorporated APPLICATION INFORMATION 57
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