Datasheet

LD(n) LD (n+1)
BIT
CLOCK
DATA
-
1
-
2
-
3
2 1 03 -
1
-
2
-
3
03 2 1 -
1
-
2
N N N N N N N N N
-
3
3
RD(n)
WORD
CLOCK
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
LD(n) LD(n+1)
BIT
CLOCK
DATA
-
1
-
2
-
3
2 1 03 -
1
-
2
-
3
03 2 1 -
1
-
2
N N N N N N N N N
-
3
RD(n)
WORD
CLOCK
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
LD(n) LD(n+1)
BIT
CLOCK
DATA
N
-
1
N
-
2
N
-
3
2 1 0
3
N
-
1
N
-
2
N
-
3
03 2 1
N
-
1
N
-
2
N
-
3
3
RD(n)
WORD
CLOCK
LEFT CHANNEL RIGHT CHANNEL
TLV320DAC3100
SLAS671A –FEBRUARY 2010–REVISED MAY 2012 www.ti.com
Figure 5-31. Timing Diagram for DSP Mode
Figure 5-32. Timing Diagram for DSP Mode With Offset = 1
Figure 5-33. Timing Diagram for DSP Mode With Offset = 0 and Bit Clock Inverted
For the DSP mode, the number of bit clocks per frame should be greater than or equal to twice the
programmed word length of the data. Also, the programmed offset value should be less than the number
of bit clocks per frame by at least the programmed word length of the data.
5.7.2 Primary and Secondary Digital Audio Interface Selection
The audio serial interface on the TLV320DAC3100 has extensive I/O control to allow communication with
two independent processors for audio data. The processors can communicate with the device one at a
time. This feature is enabled by register programming of the various pin selections. Table 5-29 shows the
primary and secondary audio interface selection and registers. Figure 5-34 is a high-level diagram
showing the general signal flow and multiplexing for the primary and secondary audio interfaces.
Table 5-29. Primary and Secondary Audio Interface Selection
Desired Pin Possible
Page 0 Registers Comment
Function Pins
R27/D2 = 1 Primary WCLK is output from codec
Primary WCLK
WCLK
(OUT)
R33/D5–D4 Select source of primary WCLK (DAC_fs or secondary WCLK)
56 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated
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