Datasheet

LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2 1 03 -
1
-
2
-
3
2 1 03 -
1
-
2
N N N N N N N N N
-
3
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
LD(n) LD (n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
4 3 25 1 0 -
1
4 3 25 1 0
N N N
-
1
5
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2 1 03 -
1
-
2
-
3
2 1 03 -
1
-
2
N N N N N N N N N
-
3
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
TLV320DAC3100
www.ti.com SLAS671A –FEBRUARY 2010–REVISED MAY 2012
Figure 5-28. Timing Diagram for I
2
S Mode
Figure 5-29. Timing Diagram for I
2
S Mode With Offset = 2
Figure 5-30. Timing Diagram for I
2
S Mode With Offset = 0 and Bit Clock Inverted
For I
2
S mode, the number of bit clocks per channel should be greater than or equal to the programmed
word length of the data. Also, the programmed offset value should be less than the number of bit clocks
per frame by at least the programmed word length of the data.
5.7.1.4 DSP Mode
The audio interface of the TLV320DAC3100 can be put into DSP mode by programming page 0 /
register 27, bits D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with
the left-channel data first and immediately followed by the right-channel data. Each data bit is valid on the
falling edge of the bit clock.
Copyright © 2010–2012, Texas Instruments Incorporated APPLICATION INFORMATION 55
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