Datasheet

LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2 1 03 -
1
-
2
-
3
2 1 03 -
1
-
2
N N N N N N N N N
-
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2 1 03 -
1
-
2
-
3
2 1 03 -
1
-
2
N N N N N N N N N
-
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
3
N
-
1
N
-
2
N
-
3
2 1 0
3
N
-
1
N
-
2
N
-
3
2 1 0
3
N
-
1
N
-
2
N
-
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
TLV320DAC3100
SLAS671A –FEBRUARY 2010–REVISED MAY 2012 www.ti.com
Figure 5-25. Timing Diagram for Left-Justified Mode
Figure 5-26. Timing Diagram for Left-Justified Mode With Offset = 1
Figure 5-27. Timing Diagram for Left-Justified Mode With Offset = 0 and Inverted Bit Clock
For the left-justified mode, the number of bit clocks per frame should be greater than or equal to twice the
programmed word length of the data. Also, the programmed offset value should be less than the number
of bit clocks per frame by at least the programmed word length of the data.
5.7.1.3 I
2
S Mode
The audio interface of the TLV320DAC3100 can be put into I
2
S mode by programming page 0 /
register 27, bits D7–D6 = 00. In I
2
S mode, the MSB of the left channel is valid on the second rising edge
of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on
the second rising edge of the bit clock after the rising edge of the word clock.
54 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated
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