Datasheet

BCLK
WCLK
1
00
1
0
T0149-05
1/f
S
LSBMSB
Left Channel
Right Channel
2 2
DIN
n–1 n–1n–2 n–2n–3
n–3
TLV320DAC3100
www.ti.com SLAS671A –FEBRUARY 2010–REVISED MAY 2012
The TLV320DAC3101 also includes a feature to offset the position of start-of-data-transfer with respect to
the word clock. This offset can be controlled in terms of number of bit clocks and can be programmed in
page 0 / register 28.
The TLV320DAC3101 also has the feature of inverting the polarity of the bit clock used for transferring the
audio data as compared to the default clock polarity used. This feature can be used independently of the
mode of audio interface chosen. This can be configured via page 0 / register 29, bit D3.
By default, when the word clocks and bit clocks are generated by the TLV320DAC3101, these clocks are
active only when the DAC is powered up within the device. This is done to save power. However, it also
supports a feature whereby both the word clocks and bit clocks can be active even when the codec in the
device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus,
or when word clocks or bit clocks are used in the system as general-purpose clocks.
5.7.1.1 Right-Justified Mode
The audio interface of the TLV320DAC3101 can be put into the right-justified mode by programming
page 0 / register 27, bits D7–D6 = 10. In right-justified mode, the LSB of the left channel is valid on the
rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right
channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.
Figure 5-24. Timing Diagram for Right-Justified Mode
For the right-justified mode, the number of bit clocks per frame should be greater than or equal to twice
the programmed word length of the data.
5.7.1.2 Left-Justified Mode
The audio interface of the TLV320DAC3100 can be put into left-justified mode by programming page 0 /
register 27, bits D7–D6 = 11. In left-justified mode, the MSB of the right channel is valid on the rising edge
of the bit clock following the falling edge of the word clock. Similarly, the MSB of the left channel is valid
on the rising edge of the bit clock following the rising edge of the word clock.
Copyright © 2010–2012, Texas Instruments Incorporated APPLICATION INFORMATION 53
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