Datasheet

Internal
Oscillator
÷8
0
1
P3/R16, Bits D6-D0
MCLK
P3/R16, Bit D7
Interval timers
Programmable
Divider
Powered on if
internal oscillator is
selected
Used for de-bounce time for
headset detection logic,
various power up timers and
for generation of interrupts
TLV320DAC3100
SLAS671A –FEBRUARY 2010–REVISED MAY 2012 www.ti.com
Table 5-28. PLL Example Configurations (continued)
PLL_CLKIN (MHz) PLLP PLLR PLLJ PLLD MDAC NDAC DOSR
f
S
= 44.1 kHz
48 4 1 7 1680 7 2 128
5.6.2 Timer
The internal clock runs nominally at 8.2 MHz. This is used for various internal timing intervals, de-bounce
logics and interrupts. The MCLK divider must be set such a way that the divider output is ~1 MHz for the
timers to be closer to the programmed value.
Figure 5-23. Interval Timer Clock Selection
5.7 Digital Audio and Control Interface
5.7.1 Digital Audio Interface
Audio data is transferred between the host processor and the TLV320DAC3100 via the digital audio data
serial interface, or audio bus. The audio bus on this device is very flexible, including left- or right-justified
data options, support for I
2
S or PCM protocols, programmable data-length options, a TDM mode for
multichannel operation, very flexible master/slave configurability for each bus-clock line, and the ability to
communicate directly with multiple devices within a system.
The audio bus of the TLV320DAC3100 can be configured for left- or right-justified, I
2
S, DSP, or TDM
modes of operation, where communication with standard telephony PCM interfaces is supported within the
TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by
configuring page 0 / register 27, bits D5–D4. In addition, the word clock and bit clock can be
independently configured in either master or slave mode for flexible connectivity to a wide variety of
processors. The word clock is used to define the beginning of a frame, and may be programmed as either
a pulse or a square-wave signal. The frequency of this clock corresponds to the DAC sampling frequency.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in master
mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider
in page 0 / register 30 (see Figure 5-20). The number of bit-clock pulses in a frame may need adjustment
to accommodate various word lengths, as well as to support the case when multiple TLV320DAC3101s
may share the same audio bus.
52 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated
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