Datasheet

PLL _ CLKIN
512 kHz 20 MHz
P
£ £
PLL _ CLKIN
10 MHz 20 MHz
P
£ £
TLV320DAC3100
www.ti.com SLAS671A –FEBRUARY 2010–REVISED MAY 2012
The PLL can be turned on via page 0 / register 5, bit D7. The variable P can be programmed via page 0 /
register 5, bits D6–D4. The variable R can be programmed via page 0 / register 5, bits D3–D0. The
variable J can be programmed via page 0 / register 6, bits D5–D0. The variable D is 14 bits and is
programmed into two registers. The MSB portion can be programmed via page 0 / register 7, bits D5–D0,
and the LSB portion is programmed via page 0 / register 8, bits D7–D0. For proper update of the D divider
value, page 0 / register 7 must be programmed first, followed immediately by page 0 / register 8. Unless
the write to page 0 / register 8 is completed, the new value of D does not take effect.
When the PLL is enabled, the following conditions must be satisfied:
• When the PLL is enabled and D = 0, the following conditions must be satisfied for PLL_CLKIN:
80 MHz ≤ (PLL_CLKIN × J.D × R/P)≤ 110 MHz
4 ≤ R × J ≤ 259
(7)
• When the PLL is enabled and D ≠ 0, the following conditions must be satisfied for PLL_CLKIN:
80 MHz ≤ PLL_CLKIN × J.D × R/P ≤ 110 MHz
R = 1
(8)
The PLL can be powered up independently from the DAC block, and can also be used as a general-
purpose PLL by routing its output to the GPIO output. After powering up the PLL, PLL_CLK is available
typically after 10 ms.
The clock for the codec and various signal processing blocks, CODEC_CLKIN, can be generated from the
MCLK input, BCLK input, GPIO input, or PLL_CLK (page 0 / register 4, bits D1–D0).
If CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down last.
Table 5-28 lists several example cases of typical PLL_CLKIN rates and how to program the PLL to
achieve a sample rate f
S
of either 44.1 kHz or 48 kHz.
Table 5-28. PLL Example Configurations
PLL_CLKIN (MHz) PLLP PLLR PLLJ PLLD MDAC NDAC DOSR
f
S
= 44.1 kHz
2.8224 1 3 10 0 3 5 128
5.6448 1 3 5 0 3 5 128
12 1 1 7 560 3 5 128
13 1 1 6 3504 6 3 104
16 1 1 5 2920 3 5 128
19.2 1 1 4 4100 3 5 128
48 4 1 7 560 3 5 128
f
S
= 48 kHz
2.048 1 3 14 0 7 2 128
3.072 1 4 7 0 7 2 128
4.096 1 3 7 0 7 2 128
6.144 1 2 7 0 7 2 128
8.192 1 4 3 0 4 4 128
12 1 1 7 1680 7 2 128
16 1 1 5 3760 7 2 128
19.2 1 1 4 4800 7 2 128
Copyright © 2010–2012, Texas Instruments Incorporated APPLICATION INFORMATION 51
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