Datasheet

÷N

BCLK

DAC_CLK DAC_MOD_CLK

BDIV_CLKIN

N = 1, 2, ..., 127, 128

B0362-01

TLV320DAC3100

www.ti.com

SLAS671A –FEBRUARY 2010–REVISED MAY 2012

The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel,

DAC_MOD_CLK must be enabled by configuring the NDAC and MDAC clock dividers (page 0 /

device internally initiates a power-down sequence for proper shutdown. During this shutdown sequence,

the NDAC and MDAC dividers must not be powered down, or else a proper low-power shutdown may not

take place. The user can read back the power-status flag at page 0 / register 37, bit D7 and page 0 /

followed by the NDAC divider.

In general, for proper operation, all the root clock dividers should be powered down only after the child

clock dividers have been powered down.

The TLV320DAC3100 also has options for routing some of the internal clocks to the GPIO1 pin to be used

as general-purpose clocks in the system. The feature is shown in Figure 5-22.

Figure 5-21. BCLK Output Options

In the mode when the TLV320DAC3100 is configured to drive the BCLK pin (page 0 / register 27,

bit D3 = 1), it can be driven as the divided value of BDIV_CLKIN. The division value can be programmed

in page 0 / register 30, bits D6–D0 from 1 to 128. BDIV_CLKIN can itself be configured to be one of

DAC_CLK (DAC processing clock), DAC_MOD_CLK by configuring the BDIV_CLKIN multiplexer in page

0 / register 29, bits D1–D0. Additionally, a general-purpose clock can be driven out on GPIO1.

This clock can be a divided-down version of CDIV_CLKIN. The value of this clock divider can be

programmed from 1 to 128 by writing to page 0 / register 26, bits D6–D0. CDIV_CLKIN can itself be

programmed as one of the clocks among the list shown in Figure 5-22. This can be controlled by

programming the multiplexer in page 0 / register 25, bits D2–D0.

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