Datasheet

PLL
´ ´(R J.D)/P
PLL_CLKIN
CODEC_CLKIN
DAC_MOD_CLK
DAC_CLK
NDAC =1,2,...,127,128
MDAC =1,2,...,127,128
DOSR =1,2,...,1023,1024
MCLK
BCLK
GPIO1
DIN
MCLK
BCLK
GPIO1
PLL_CLK
¸ MDAC
¸ DOSR
¸ NDAC
ToDACMAC
DAC_f
S
B0357-04
S
CODEC _ CLKIN
DAC _ f
NDAC MDAC DOSR
=
´ ´
CODEC _ CLKIN
DAC _ MOD _ CLK
NDAC MDAC
=
´
TLV320DAC3100
SLAS671A –FEBRUARY 2010–REVISED MAY 2012 www.ti.com
Figure 5-20. Clock Distribution Tree
(5)
Table 5-26. CODEC CLKIN Clock Dividers
Divider Bits
NDAC Page 0 / register 11, bits D6–D0
MDAC Page 0 / register 12, bits D6–D0
DOSR Page 0 / register 13, bits D1–D0 and page 0 / register 14, bits D7–D0
48 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated
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