Datasheet
DAC_L
DAC_R
24 dB to Mute
24 dB to Mute
Digital
Digital
7- Bit ADC
AVDD
P1
AVSS
R1
R2
18 dB to Mute
24 dB to Mute
D-
DAC
S
D-
DAC
S
Volume Level
Register Controlled
Vol
Ctl
Vol
Ctl
B0210-08
VREF
IN
AVDD
C
VOL
Tone Generator and Mixer Are
NOT Shown
VOL/
MICDET
Processing
Blocks
Processing
Blocks
TLV320DAC3100
SLAS671A –FEBRUARY 2010–REVISED MAY 2012
www.ti.com
The VOL/MICDET pin connection and functionality are shown in Figure 5-17.
Figure 5-17. Digital Volume Controls for Beep Generator and DAC Play Data
As shown in Table 5-18, the VOL/MICDET pin has a range of volume control from 18 dB down to –63 dB,
and mute. However, if less maximum gain is required, then a smaller range of voltage should be applied
to the VOL/MICDET pin. This can be done by increasing the value of R2 relative to the value of (P1 + R1),
so that more voltage is available at the bottom of P1. The circuit should also be designed such that for the
values of R1, R2, and P1 chosen, the maximum voltage (top of the potentiometer) does not exceed
AVDD/2 (see Figure 5-17). The recommended values for R1, R2, and P1 for several maximum gains are
shown in Table 5-19.
Table 5-19. VOL/MICDET Pin Gain Scaling
ADC VOLTAGE
R1 P1 R2 DIGITAL GAIN RANGE
for AVDD = 3.3 V
(kΩ) (kΩ) (kΩ) (dB)
(V)
25 25 0 0 V to 1.65 V 18 dB to –63 dB
33 25 7.68 0.386 V to 1.642 V 3 dB to –63 dB
34.8 25 9.76 0.463 V to 1.649 V 0 dB to –63 dB
5.5.4 Dynamic Range Compression
Typical music signals are characterized by crest factors, the ratio of peak signal power to average signal
power, of 12 dB or more. To avoid audible distortions due to clipping of peak signals, the gain of the DAC
channel must be adjusted so as not to cause hard clipping of peak signals. As a result, during nominal
periods, the applied gain is low, causing the perception that the signal is not loud enough. To overcome
this problem, dynamic range conpression (DRC) in the TLV320DAC3101 continuously monitors the output
of the DAC digital volume control to detect its power level relative to 0 dBFS. When the power level is low,
DRC increases the input signal gain to make it sound louder. At the same time, if a peaking signal is
detected, it autonomously reduces the applied gain to avoid hard clipping. This results in sounds more
pleasing to the ear, as well as sounding louder during nominal periods.
The DRC functionality in the TLV320DAC3101 is implemented by a combination of processing blocks in
the DAC channel as described in Section 5.5.1.2.
DRC can be disabled by writing to page 0 / register 68, bits D6–D5.
32 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated
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