Datasheet

STO
STA STA
STO
SDA
SCL
t
BUF
t
LOW
t
SU;STA
t
HIGH
t
HD;STA
t
r
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
f
T0295-02
TLV320DAC3100
www.ti.com SLAS671A –FEBRUARY 2010–REVISED MAY 2012
3.4.5 I
2
C Interface Timing
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization.
Standard Mode Fast Mode
PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
f
SCL
SCL clock frequency 0 100 0 400 kHz
Hold time, (repeated) START condition.
t
HD;STA
After this period, the first clock pulse is 4 0.8 μs
generated.
t
LOW
LOW period of the SCL clock 4.7 1.3 μs
t
HIGH
HIGH period of the SCL clock 4 0.6 μs
Setup time for a repeated START
t
SU;STA
4.7 0.8 μs
condition
t
HD;DAT
Data hold time: for I
2
C bus devices 0 3.45 0 0.9 μs
t
SU;DAT
Data set-up time 250 100 ns
t
r
SDA and SCL rise time 1000 20 + 0.1C
b
300 ns
t
f
SDA and SCL fall time 300 20 + 0.1C
b
300 ns
t
SU;STO
Set-up time for STOP condition 4 0.8 μs
Bus free time between a STOP and
t
BUF
4.7 1.3 μs
START condition
C
b
Capacitive load for each bus line 400 400 pF
Figure 3-5. I
2
C Interface Timing
Copyright © 2010–2012, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 11
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