Datasheet

3−7
3.3.1.4 DSP Mode
The DSP mode is compatible with the McBSP ports of TI DSPs. LRCIN must be connected to the Frame Sync signal
of the McBSP. A falling edge on LRCIN starts the data transfer. The left-channel data consists of the first data word,
which is immediately followed by the right channel data word (see Figure 3-7).
LRCIN
BCLK
DIN
n n−1 01 n−1n
Left Channel Right Channel
1 0
MSB LSB MSB LSB
Figure 3−7. DSP Mode Timing
3.3.2 Audio Sampling Rates
The TLV320DAC23 can operate in master or slave clock mode. In the master mode, the TLV320DAC23 clock and
sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock signal is compatible with the USB
specification. The TLV320DAC23 can be used directly in a USB system.
In the slave mode, the TLV320DAC23 clock and sample rates are controlled by using an appropriate MCLK or crystal
frequency and the sample rate control register settings.
The settings in the sample rate control register control the clock mode and sampling rates.
Sample Rate Control (Address: 0001000)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal
Default 0 0 0 0 0 0 0 0 0
CLKOUT Clock output divider 0 = MCLK 1 = MCLK/2
CLKIN Clock input divider 0 = MCLK 1 = MCLK/2
SR[3:0] Sample rate control (see Sections 3.3.2.1 and 3.3.2.2)
BOSR Base oversampling rate
USB mode: 0 = 250 f
s
1 = 272 f
s
Normal mode: 0 = 256 f
s
1 = 384 f
s
USB/Normal
Clock mode select: 0 =Normal 1 =USB
X Reserved
The clock circuit of the DAC23 has two internal dividers. The first, controlled by CLKIN, applies to the sampling-rate
generator of the DAC. The second, controlled by CLKOUT, applies only to the CLKOUT terminal. By setting CLKIN
to 1, the entire DAC is clocked with half the frequency, effectively dividing the resulting sampling rates by two.