Datasheet

3−5
The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to standby mode,
the line inputs are kept biased to VMID using special antithump circuitry. This reduces audible clicks that otherwise
might be heard when reactivating the inputs.
For interfacing to a CD system, the line input should be scaled to 1 V
RMS
to avoid clipping, using the circuit shown
in Figure 3-3.
R
2
R1
C1
C2 +
CDIN LINEIN
AGND
Where:
R1 = 5 kΩ
R2 = 5 kΩ
C1 = 47 pF
C2 = 470 nF
Figure 3−3. Analog Line Input Circuit
R1 and R2 divide the input signal by two, reducing the 2 V
RMS
from the CD player to the nominal 1 V
RMS
of the DAC23
inputs. C1 filters high-frequency noise, and C2 removes any dc component from the signal.
3.2.2 Line Outputs
The TLV320DAC23 has two low-impedance line outputs (LLINEOUT and RLINEOUT) capable of driving line loads
with 10-kΩ and 50-pF impedances.
The DAC full-scale output voltage is 1.0 V
RMS
at AV
DD
= 3.3 V. The full-scale range tracks linearly with the analog
supply voltage AV
DD.
The DAC is connected to the line outputs via a low-pass filter that removes out-of-band
components. No further external filtering is required in most applications.
The DAC outputs and the line inputs are summed into the line outputs. The line outputs are muted by either muting
the DAC (analog) or soft muting (digital) and disabling the bypass path (see Section 3.1.3).
3.2.3 Headphone Output
The TLV320DAC23 has stereo headphone outputs (LHPOUT and RHPOUT), and is designed to drive 16-Ω or 32-Ω
headphones. The headphone output includes a high-quality volume control and mute function.
The headphone volume is logarithmically adjustable from 6 dB to –73 dB in 1-dB steps. Writing 000000 to the
volume-control registers (see Section 3.1.3) mutes the headphone output. When the headphone output is muted or
the device is placed in standby mode, the dc voltage is maintained at the outputs to prevent audible clicks.
A zero-cross detection circuit is provided under the control of the LZC and RZC bits. If this circuit is enabled, the
volume-control values are updated only when the input signal to the gain stage is close to the analog ground level.
This minimizes audible clicks as the volume is changed or the device is muted. This circuit has no time-out, so if only
dc levels are being applied to the gain stage input of more than 20 mV, the gain is not updated.
The gain is independently programmable on the left and right channels. Both channels can be locked to the same
value by setting the RLS and LRS bits (see Section 3.1.3).
3.3 Digital Audio Interface
3.3.1 Digital Audio-Interface Modes
The TLV320DAC23 supports four audio-interface modes.
• Right justified
• Left justified
• I
2
S mode
• DSP mode