Datasheet

2−6
2.4.3 Three-Wire Control Interface (SDI)
PARAMETER MIN TYP MAX UNIT
t
w(5)
Clock pulse duration, SCLK
High 20
ns
t
w(6)
Clock pulse duration, SCLK
Low 20
ns
t
c(3)
Clock period, SCLK 80 ns
t
su(4)
Clock rising edge to CS rising edge, SCLK 60 ns
t
su(5)
Setup time, SDIN to SCLK 20 ns
t
h(4)
Hold time, SCLK to SDIN 20 ns
t
w(7)
Pulse duration, CS
High 20
ns
t
w(8)
Pulse duration, CS
Low 20
ns
LSB
t
w(8)
t
c(3)
t
w(6)
t
w(5)
t
su(4)
t
h(4)
t
su(5)
CS
SCLK
DIN
Figure 2−4. Three-Wire Control Interface Timing Requirements
2.4.4 Two-Wire Control Interface
PARAMETER MIN TYP MAX UNIT
t
w(9)
Clock pulse duration, SCLK
High 1.3 µs
t
w(10)
Clock pulse duration, SCLK
Low 600 ns
f(sf) Clock frequency, SCLK 0 400 kHz
t
h(5)
Hold time (start condition) 600 ns
t
su(6)
Setup time (start condition) 600 ns
t
h(6)
Data hold time 900 ns
t
su(7)
Data setup time 100 ns
t
r
Rise time, SDIN, SCLK 300 ns
t
f
Fall time, SDIN, SCLK 300 ns
t
su(8)
Setup time (stop condition) 600 ns
SCLK
DIN
t
w(9)
t
w(10)
t
h(5)
t
h(6)
t
su(7)
t
su(8)
Figure 2−5. Two-Wire Control Interface Timing Requirements