Datasheet

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TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Page 0 / Register 12: Audio Codec Digital Filter Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 – D6 R/W 00 Left-ADC High-Pass Filter Control
00: Left-ADC high-pass filter disabled
01: Left-ADC high-pass filter – 3-dB frequency = 0.0045 × ADC f
S
10: Left-ADC high-pass filter – 3-dB frequency = 0.0125 × ADC f
S
11: Left-ADC high-pass filter – 3-dB frequency = 0.025 × ADC f
S
D5 – D4 R/W 00 Right-ADC High-Pass Filter Control
00: Right-ADC high-pass filter disabled
01: Right-ADC high-pass filter – 3-dB frequency = 0.0045 × ADC f
S
10: Right-ADC high-pass filter – 3-dB frequency = 0.0125 × ADC f
S
11: Right-ADC high-pass filter – 3-dB frequency = 0.025 × ADC f
S
D3 R/W 0 Left-DAC Digital Effects Filter Control
0: Left-DAC digital effects filter disabled (bypassed)
1: Left-DAC digital effects filter enabled
D2 R/W 0 Left-DAC De-Emphasis Filter Control
0: Left-DAC de-emphasis filter disabled (bypassed)
1: Left-DAC de-emphasis filter enabled
D1 R/W 0 Right-DAC Digital Effects Filter Control
0: Right-DAC digital effects filter disabled (bypassed)
1: Right-DAC digital effects filter enabled
D0 R/W 0 Right-DAC De-Emphasis Filter Control
0: Right-DAC de-emphasis filter disabled (bypassed)
1: Right-DAC de-emphasis filter enabled
Page 0 / Register 13: Headset / Button Press Detection Register A
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 Headset Detection Control
0: Headset detection disabled
1: Headset detection enabled
D6 – D5 R 00 Headset Type Detection Results
00: No headset detected
01: Headset without microphone detected
10: Ignore (reserved)
11: Headset with microphone detected
D4 – D2 R/W 000 Headset Glitch Suppression Debounce Control for Jack Detection
000: Debounce = 16 ms (sampled with 2-ms clock)
001: Debounce = 32 ms (sampled with 4-ms clock)
010: Debounce = 64 ms (sampled with 8-ms clock)
011: Debounce = 128 ms (sampled with 16-ms clock)
100: Debounce = 256 ms (sampled with 32-ms clock)
101: Debounce = 512 ms (sampled with 64-ms clock)
110 – 111: Reserved. Do not write these sequences to these register bits.
D1 – D0 R/W 00 Headset Glitch Suppression Debounce Control for Button Press
00: Debounce = 0 ms
01: Debounce = 8 ms (sampled with 1-ms clock)
10: Debounce = 16 ms (sampled with 2-ms clock)
11: Debounce = 32 ms (sampled with 4-ms clock)
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