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Decay Time
Target
Level
Input
Signal
Output
Signal
AGC
Gain
Attack
Time
STEREO AUDIO DAC
TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Figure 27. Typical Operation of the AGC Algorithm During Speech Recording
Note that the time constants here are correct when the ADC is not in double-rate audio mode. The time
constants are achieved using the f
S(ref)
value programmed in the control registers. However, if the f
S(ref)
is set in
the registers to, for example, 48 kHz, but the actual audio clock or PLL programming actually results in a different
f
S(ref)
in practice, then the time constants would not be correct. See The Built-In AGC Function in TSC2100/01
and TLV320AIC26/28/32/33 Devices application report (SLAA260 ).
The TLV320AIC34 includes a stereo audio DAC in each partition supporting sampling rates from 8 kHz to
96 kHz. Each channel of the audio DACs consists of a digital audio processing block, a digital interpolation filter,
multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide
enhanced performance at low sampling rates through increased oversampling and image filtering, thereby
keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed
within the audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 × f
S(ref)
and changing the oversampling ratio as the input sample rate is changed. For an f
S(ref)
of 48 kHz, the digital
delta-sigma modulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated
within the delta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly,
for an f
S(ref)
rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.
The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is
enabled in the DAC.
Allowed Q values = 4, 8, 9, 12, 16
Q values where equivalent f
S(ref)
can be achieved by turning on PLL
Q = 5, 6, 7 (set P = 5 / 6 / 7 and K = 16.0 and PLL enabled)
Q = 10, 14 (set P = 5, 7 and K = 8.0 and PLL enabled)
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