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STEREO AUDIO ADC

STEREO AUDIO ADC HIGH-PASS FILTER

H(z) +

N0 ) N1 z

32768 * D1 z

(1)

DIGITAL AUDIO PROCESSING FOR RECORD PATH

TLV320AIC34

SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007

The partition of the TLV320AIC34 includes a stereo audio ADC, which uses a delta-sigma modulator with

128-times oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling

rates from 8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC

is in operation, the device requires that an audio master clock be provided and appropriate audio clock

generation be setup within the part.

In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to

support the case where only mono record capability is required. In addition, both channels can be fully powered

or entirely powered down.

The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an

initial sampling rate of 128 f

to the final output sampling rate of f

. The decimation filter provides a linear phase

output response with a group delay of 17/f

. The – 3-dB bandwidth of the decimation filter extends to 0.45 f

and

scales with the sample rate (f

). The filter has minimum 75-dB attenuation over the stopband from 0.55 f

to 64

. Independent digital high-pass filters are also included with each ADC channel, with a corner frequency that

can be independently set to three different settings, can be disabled entirely, or can be programmed to a

completely customized transfer function, as described in the following section.

Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,

requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC34 integrates a second-order

analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter,

provides sufficient anti-aliasing filtering without requiring additional external components.

The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to

59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that

only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on

the register programming (see page 0, registers 19 and 22). This soft-stepping ensures that volume control

changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on

power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the

gain applied by the PGA equals the desired value set by the register. The soft-stepping control can also be

disabled by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to

the part after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When

the ADC power-down flag is no longer set, the audio master clock can be shut down.

Often in audio applications it is desirable to remove the dc offset from the converted audio data stream. The

TLV320AIC34 has a programmable first-order, high-pass filter that can be used for this purpose. The digital filter

coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients, N0, N1,

and D1. The transfer function of the digital high-pass filter is of the form:

Programming the left channel is done by writing to page 1, registers 65 – 70, and the right channel is programmed

by writing to page 1, registers 71 – 76. After the coefficients have been loaded, these ADC high-pass filter

coefficients can be selected by writing to page 0, register 107, D7 – D6, and the high-pass filter can be enabled by

writing to page 0, register 12, bits D7 – D4.

In applications where record- only is selected in a particular partition, and the DAC in that partition is powered

down, the playback path signal processing blocks can be used in the ADC record path. These filtering blocks can

support high-pass, low-pass, band-pass, or notch filtering, or an entirely arbitrary transfer function. In this mode,

the record-only path has switches SW-D1 through SW-D4 closed and reroutes the ADC output data through the

digital signal processing blocks. Because the DAC digital signal processing blocks are being re-used, naturally

the addresses of these digital filter coefficients are the same as for the DAC digital processing and are located on

page 1, registers 1 – 52. This record-only mode is enabled by powering down both DACs by writing to page 0,

for one partition can be seen in Figure 26 .

Product Folder Link(s): TLV320AIC34