Datasheet

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T0146-04
WCLK_x
BCLK_x
DOUT_x
DIN_x
t (WS)
h
t (WS)
h
t (BCLK)
L
t (DO-BCLK)
d
t (DI)
S
t (BCLK)
H
t (DI)
h
t (WS)
S
t (WS)
S
TLV320AIC34
SLAS538A OCTOBER 2007 REVISED NOVEMBER 2007
All specifications at 25 ° C, DVDD = 1.8 V
IOVDD = 1.1 V IOVDD = 3.3 V
PARAMETER UNIT
MIN MAX MIN MAX
t
H
(BCLK) BCLK_x high period 70 35 ns
t
L
(BCLK) BCLK_x low period 70 35 ns
t
s
(WS) ADWS/WCLK_x setup time 10 6 ns
t
h
(WS) ADWS/WCLK_x hold time 10 6 ns
t
d
(DO-BCLK) BCLK_x to DOUT_x delay time 50 20 ns
t
s
(DI) DIN_x setup time 10 6 ns
t
h
(DI) DIN_x hold time 10 6 ns
t
r
Rise time 8 4 ns
t
f
Fall time 8 4 ns
NOTE: All timing specifications are measured at characterization but not tested at final test.
Figure 4. DSP Timing in Slave Mode
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