Datasheet

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4.6 Clocks Tab
4.6.1 Configuring the codec clocks and Fsref calculation
TLV320AIC34EVM Software
Figure 7. Clocks Tab
The TLV320AIC34 provides a phase-locked loop (PLL) that allows flexibility in the clock generation for the
ADC and DAC sample rates. The Clocks tab contains the controls that can be used to configure the
TLV320AIC34 for operation with a wide range of master clocks. See the Audio Clock Generation
Processing figure in the TLV320AIC34 data sheet for further details of selecting the correct clock settings.
For use with the PC software and the USB-MODEVM, the clock settings must be set a certain way. If the
settings are changed from the default settings which allow operation from the USB-MODEVM clock
reference, the EVM settings can be restored automatically by pushing the Load EVM Clock Settings
button at the bottom of this tab. Note that changing any of the clock settings from the values loaded when
this button is pushed may result in the EVM not working properly with the PC software or USB interface. If
an external audio bus is used (audio not driven over the USB bus), then settings may be changed to any
valid combination. See Figure 7 .
The codec clock source is chosen by the CODEC_CLK Source control. When this control is set to
CLKDIV_OUT, the PLL is not used; when set to PLLDIV_OUT, the PLL is used to generate the clocks.
Note: Per the TLV320AIC34 data sheet, the codec should be configured to allow the value of Fsref
to fall between the values of 39kHz to 53kHz.
TLV320AIC34EVM-K 16 SLAU232 – December 2007
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