Datasheet

TLV320AIC33
www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008
Page 0 / Register 100: Additional GPIO Control Register A (continued)
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D4 R 0 SDA General Purpose Input Value
(1)
0: SDA detects a logic-low when used as general purpose input
1: SDA is detects a logic-high when used as general purpose input
D3-D2 R/W 00 SCL Pin Control
(1)
The SCL pin hardware includes pulldown capability only (open-drain NMOS), so an external pull-up
resistor is required when using this pin, even in GPIO mode.
00: SCL pin is not used as general purpose I/O
01: SCL pin used as general purpose input
10: SCL pin used as general purpose output
11: Reserved. Do not write this sequence to these register bits.
D1 R/W 0 SCL General Purpose Output Control
(1)
0: SCL driven to logic-low when used as general purpose output
1: SCL driven to logic-high when used as general purpose output (requires external pull-up resistor)
D0 R 0 SCL General Purpose Input Value
(1)
0: SCL detects a logic-low when used as general purpose input
1: SCL detects a logic-high when used as general purpose input
Page 0 / Register 101: Additional GPIO Control Register B
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R 0 I
2
C Address Pin #0 Status
(1)
0: MFP1 pin = I
2
C address pin #0 = 0 at reset
1: MFP1 pin = I
2
C address pin #0 = 1 at reset
D6 R 0 I
2
C Address Pin #1 Status
(1)
0: MFP0 pin = I
2
C address pin #1 = 0 at reset
1: MFP0 pin = I
2
C address pin #1 = 1 at reset
D5 R/W 0 MFP3 Pin General Purpose Input Control
(1)
0: MFP3 pin usage as general purpose input is disabled
1: MFP3 pin usage as general purpose input is enabled
D4 R/W 0 MFP3 Pin Serial Data Bus Input Control
(1)
0: MFP3 pin usage as audio serial data input pin is disabled
1: MFP3 pin usage as audio serial data input pin is enabled
D3 R 0 MFP3 General Purpose Input Value
(1)
0: MFP3 detects a logic-low when used as general purpose input
1: MFP3 detects a logic-high when used as general purpose input
D2 R/W 0 MFP2 General Purpose Output Control
(1)
0: MFP2 pin usage as general purpose output is disabled
1: MFP2 pin usage as general purpose output is enabled
D1 R/W 0 MFP2 General Purpose Output Control
(1)
0: MFP2 pin drives a logic-low when used as a general purpose output
1: MFP2 pin drives a logic-high when used as a general purpose output
D0 R/W 0 CODEC_CLKIN Source Selection
0: CODEC_CLKIN uses PLLDIV_OUT
1: CODEC_CLKIN uses CLKDIV_OUT
(1) Bits D7-D1 in Register 101 are only valid in I
2
C control Mode, when SELECT = 0.
Page 0 / Register 102: Clock Generation Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D6 R/W 00 CLKDIV_IN Source Selection
00: CLKDIV_IN uses MCLK
01: CLKDIV_IN uses GPIO2
10: CLKDIV_IN uses BCLK
11: Reserved. Do not use.
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