Datasheet

TLV320AIC33
www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008
Page 0 / Register 70: PGA_R to HPRCOM Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_R Output Routing Control
0: PGA_R is not routed to HPRCOM
1: PGA_R is routed to HPRCOM
D6-D0 R/W 0000000 PGA_R to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 71: DAC_R1 to HPRCOM Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPRCOM
1: DAC_R1 is routed to HPRCOM
D6-D0 R/W 0000000 DAC_R1 to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 72: HPRCOM Output Level Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D4 R/W 0000 HPRCOM Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010 – 1111: Reserved. Do not write these sequences to these register bits.
D3 R/W 0 HPRCOM Mute
0: HPRCOM is muted
1: HPRCOM is not muted
D2 R/W 1 HPRCOM Power Down Drive Control
0: HPRCOM is weakly driven to a common-mode when powered down
1: HPRCOM is tri-stated with powered down
D1 R 0 HPRCOM Volume Control Status
0: All programmed gains to HPRCOM have been applied
1: Not all programmed gains to HPRCOM have been applied yet
D0 R/W 0 HPRCOM Power Control
0: HPRCOM is not fully powered up
1: HPRCOM is fully powered up
Page 0 / Register 73: LINE2L to MONO_LOP/M Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 LINE2L Output Routing Control
0: LINE2L is not routed to MONO_LOP/M
1: LINE2L is routed to MONO_LOP/M
D6-D0 R/W 0000000 LINE2L to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 74: PGA_L to MONO_LOP/M Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_L Output Routing Control
0: PGA_L is not routed to MONO_LOP/M
1: PGA_L is routed to MONO_LOP/M
D6-D0 R/W 0000000 PGA_L to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
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