Datasheet
TLV320AIC33
SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ...........................................................................................................................................
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Page 0 / Register 10: Audio Serial Data Interface Control Register C
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 00000000 Audio Serial Data Word Offset Control
This register determines where valid data is placed or expected in each frame, by controlling
the offset from beginning of the frame where valid data begins. The offset is measured from
the rising edge of word clock when in DSP mode.
00000000: Data offset = 0 bit clocks
00000001: Data offset = 1 bit clock
00000010: Data offset = 2 bit clocks
…
Note: In continuous transfer mode the maximum offset is 17 for I
2
S/LJF/RJF modes and 16
for DSP mode. In 256-clock mode, the maximum offset is 242 for I
2
S/LJF/RJF and 241 for
DSP modes.
11111110: Data offset = 254 bit clocks
11111111: Data offset = 255 bit clocks
Page 0 / Register 11: Audio Codec Overflow Flag Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R 0 Left ADC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D6 R 0 Right ADC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D5 R 0 Left DAC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D4 R 0 Right DAC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D3 – D0 R/W 0001 PLL R Value
0000: R = 16
0001 : R = 1
0010 : R = 2
0011 : R = 3
0100 : R = 4
…
1110: R = 14
1111: R = 15
Page 0 / Register 12: Audio Codec Digital Filter Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D6 R/W 00 Left ADC Highpass Filter Control
00: Left ADC highpass filter disabled
01: Left ADC highpass filter – 3-dB frequency = 0.0045 × ADC Fs
10: Left ADC highpass filter – 3-dB frequency = 0.0125 × ADC Fs
11: Left ADC highpass filter – 3-dB frequency = 0.025 × ADC Fs
D5 – D4 R/W 00 Right ADC Highpass Filter Control
00: Right ADC highpass filter disabled
01: Right ADC highpass filter – 3-dB frequency = 0.0045 × ADC Fs
10: Right ADC highpass filter – 3-dB frequency = 0.0125 × ADC Fs
11: Right ADC highpass filter – 3-dB frequency = 0.025 × ADC Fs
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