Datasheet

2/Q
GPIO2
PLL_CLKIN
CODEC
CODEC_CLKIN
2/(N*M)
CLKMUX_OUT
GPIO1
PLL_OUT
K = J.D
J = 1,2,3,. . . , 62,63
D= 0000,0001, . . . ,9998,9999
R= 1,2,3,4, . . . ,15,16
P= 1,2, . . . . ,7,8
M =1,2,4,8
N = 2,3, . . . ., 16,17
MCLK BCLK
CLKDIV_IN
PLL_IN
WCLK= Fsref/ Ndac GPIO1= Fsref/ Nadc
ADC_FSDAC_FSCLKOUT
Ndac=1,1.5,2, . . ., 5.5,6
DAC DRA => Ndac = 0.5
ADC DRA => Nadc = 0.5
CODEC_CLK=256*Fsref
CLKOUT_IN
CLKDIV_OUT
1/8
PLLDIV_OUT
CLKDIV_CLKIN
Q = 3,3, . . . . ,16,17
K*R/P
Ndac=1,1.5,2, . . ., 5.5,6
TLV320AIC33
SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com
Figure 27. Audio Clock Generation Processing
The part can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a
programmable divider or a PLL, to get the proper internal audio master clock needed by the part. The BCLK or
GPIO2 inputs can also be used to generate the internal audio master clock.
This design also allows the PLL to be used for an entirely separate purpose in a system, if the audio codec is not
powered up. The user can supply a separate clock to GPIO2, route this through the PLL, with the resulting output
clock driven out GPIO1, for use by other devices in the system
A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies
available in the system. This device includes a highly programmable PLL to accommodate such situations easily.
The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus
paid to the standard MCLK rates already widely used.
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