Datasheet

n-1 n-2 n-3 n-1 n-2 n-3
I
2
S MODE
n-1
n-3n-2
n-1 n-3n-2
DSP MODE
TLV320AIC33
www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008
Figure 23. Left Justified Serial Data Bus Mode Operation
In I
2
S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock.
Figure 24. I
2
S Serial Data Bus Mode Operation
In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and
immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.
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