Datasheet
Table Of Contents
- FEATURES
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT JUSTIFIED MODE
- LEFT JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- MICBIAS GENERATION
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH POWER OUTPUT DRIVERS
- SHORT CIRCUIT OUTPUT PROTECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
T0146-01
WCLK
BCLK
SDOUT
SDIN
t (DO-BCLK)
d
t (WS)
d
t (WS)
d
t (DI)
S
t (DI)
h
TLV320AIC32
www.ti.com
............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008
All specifications at 25 ° C, DVDD = 1.8 V.
IOVDD = 1.1 V IOVDD = 3.3 V
PARAMETER UNIT
MIN MAX MIN MAX
t
d
(WS) ADWS/WCLK delay time 50 15 ns
t
d
(DO-BCLK) BCLK to DOUT delay time 50 15 ns
t
s
(DI) DIN setup time 10 6 ns
t
h
(DI) DIN hold time 10 6 ns
t
r
Rise time 30 10 ns
t
f
Fall time 30 10 ns
NOTE: All timing specifications are measured at characterization but not tested at final test.
Figure 3. DSP Timing in Master Mode
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