Datasheet
Table Of Contents
- FEATURES
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT JUSTIFIED MODE
- LEFT JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- MICBIAS GENERATION
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH POWER OUTPUT DRIVERS
- SHORT CIRCUIT OUTPUT PROTECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
TLV320AIC32
www.ti.com
............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008
Page 0 / Register 97: Real-time Interrupt Flags Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R 0 HPLOUT Short Circuit Detection Status
0: No short circuit detected at HPLOUT driver
1: Short circuit detected at HPLOUT driver
D6 R 0 HPROUT Short Circuit Detection Status
0: No short circuit detected at HPROUT driver
1: Short circuit detected at HPROUT driver
D5 R 0 HPLCOM Short Circuit Detection Status
0: No short circuit detected at HPLCOM driver
1: Short circuit detected at HPLCOM driver
D4 R 0 HPRCOM Short Circuit Detection Status
0: No short circuit detected at HPRCOM driver
1: Short circuit detected at HPRCOM driver
D3-D2 R 00 Reserved. Write only 00 to these bits.
D1 R 0 Left ADC AGC Noise Gate Status
0: Left ADC Signal Power Greater than Noise Threshold for Left AGC
1: Left ADC Signal Power Lower than Noise Threshold for Left AGC
D0 R 0 Right ADC AGC Noise Gate Status
0: Right ADC Signal Power Greater than Noise Threshold for Right AGC
1: Right ADC Signal Power Lower than Noise Threshold for Right AGC
Page 0 / Register 98 – 100: Reserved Registers
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D0 R/W 00000000 Reserved. Write only 00000000 to these bits.
Page 0 / Register 101: Additional Clock Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D1 R/W 0000000 Reserved. Write only 0000000 to these bits.
D0 R/W 0 CODEC_CLKIN Source Selection
0: CODEC_CLKIN uses PLLDIV_OUT
1: CODEC_CLKIN uses CLKDIV_OUT
Page 0 / Register 102: Clock Generation Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D6 R/W 00 CLKDIV_IN Source Selection
00: CLKDIV_IN uses MCLK
01: Reserved. Do not use.
10: CLKDIV_IN uses BCLK
11: Reserved. Do not use.
D5-D4 R/W 00 PLLCLK_IN Source Selection
00: PLLCLK_IN uses MCLK
01: Reserved. Do not use.
10: PLLCLK _IN uses BCLK
11: Reserved. Do not use.
D3-D0 R/W 0010 Reserved. Write only 0010 to these bits.
Page 0 / Register 103 – 127: Reserved Registers
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D0 R 00000000 Reserved. Do not write to these registers.
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