Datasheet
Table Of Contents
- FEATURES
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT JUSTIFIED MODE
- LEFT JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- MICBIAS GENERATION
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH POWER OUTPUT DRIVERS
- SHORT CIRCUIT OUTPUT PROTECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
TLV320AIC32
www.ti.com
............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008
Table 5. Output Stage Volume Control Settings and Gains (continued)
Gain Setting Analog Gain Gain Setting Analog Gain Gain Setting Analog Gain Gain Setting Analog Gain
(dB) (dB) (dB) (dB)
15 -7.5 45 -22.6 75 -37.7 105 -52.7
16 -8.0 46 -23.1 76 -38.2 106 -53.7
17 -8.5 47 -23.6 77 -38.7 107 -54.2
18 -9.0 48 -24.1 78 -39.2 108 -55.3
19 -9.5 49 -24.6 79 -39.7 109 -56.7
20 -10.0 50 -25.1 80 -40.2 110 -58.3
21 -10.5 51 -25.6 81 -40.7 111 -60.2
22 -11.0 52 -26.1 82 -41.2 112 -62.7
23 -11.5 53 -26.6 83 -41.7 113 -64.3
24 -12.0 54 -27.1 84 -42.2 114 -66.2
25 -12.5 55 -27.6 85 -42.7 115 -68.7
26 -13.0 56 -28.1 86 -43.2 116 -72.2
27 -13.5 57 -28.6 87 -43.8 117 -78.3
28 -14.0 58 -29.1 88 -44.3 118 – 127 Mute
29 -14.5 59 -29.6 89 -44.8
Page 0 / Register 45: LINE2L to HPLOUT Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 LINE2L Output Routing Control
0: LINE2L is not routed to HPLOUT
1: LINE2L is routed to HPLOUT
D6-D0 R/W 0000000 LINE2L to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5
Page 0 / Register 46: PGA_L to HPLOUT Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_L Output Routing Control
0: PGA_L is not routed to HPLOUT
1: PGA_L is routed to HPLOUT
D6-D0 R/W 0000000 PGA_L to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5
Page 0 / Register 47: DAC_L1 to HPLOUT Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPLOUT
1: DAC_L1 is routed to HPLOUT
D6-D0 R/W 0000000 DAC_L1 to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5
Page 0 / Register 48: LINE2R to HPLOUT Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 LINE2R Output Routing Control
0: LINE2R is not routed to HPLOUT
1: LINE2R is routed to HPLOUT
D6-D0 R/W 0000000 LINE2R to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 55
Product Folder Link(s): TLV320AIC32