Datasheet
Table Of Contents
- FEATURES
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT JUSTIFIED MODE
- LEFT JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- MICBIAS GENERATION
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH POWER OUTPUT DRIVERS
- SHORT CIRCUIT OUTPUT PROTECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
TLV320AIC32
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............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008
Page 0 / Register 35: Right AGC Noise Gate Debounce Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D3 R/W 00000 Right AGC Noise Detection Debounce Control
These times
(1)
will not be accurate when double rate audio mode is enabled.
00000: Debounce = 0-msec
00001: Debounce = 0.5-msec
00010: Debounce = 1-msec
00011: Debounce = 2-msec
00100: Debounce = 4-msec
00101: Debounce = 8-msec
00110: Debounce = 16-msec
00111: Debounce = 32-msec
01000: Debounce = 64 × 1 = 64ms
01001: Debounce = 64 × 2 = 128ms
01010: Debounce = 64 × 3 = 192ms
…
11110: Debounce = 64 × 23 = 1472ms
11111: Debounce = 64 × 24 = 1536ms
D7 – D3 R/W 00000 Right AGC Signal Detection Debounce Control
These times
(1)
will not be accurate when double rate audio mode is enabled.
000: Debounce = 0-msec
001: Debounce = 0.5-msec
010: Debounce = 1-msec
011: Debounce = 2-msec
100: Debounce = 4-msec
101: Debounce = 8-msec
110: Debounce = 16-msec
111: Debounce = 32-msec
(1) Time constants are valid when DRA is not enabled. The values would change when DRA is enabled.
Page 0 / Register 36: ADC Flag Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R 0 Left ADC PGA Status
0: Applied gain and programmed gain are not the same
1: Applied gain = programmed gain
D6 R 0 Left ADC Power Status
0: Left ADC is in a power down state
1: Left ADC is in a power up state
D5 R 0 Left AGC Signal Detection Status
0: Signal power is greater than noise threshold
1: Signal power is less than noise threshold
D4 R 0 Left AGC Saturation Flag
0: Left AGC is not saturated
1: Left AGC gain applied = maximum allowed gain for left AGC
D3 R 0 Right ADC PGA Status
0: Applied gain and programmed gain are not the same
1: Applied gain = programmed gain
D2 R 0 Right ADC Power Status
0: Right ADC is in a power down state
1: Right ADC is in a power up state
D1 R 0 Right AGC Signal Detection Status
0: Signal power is greater than noise threshold
1: Signal power is less than noise threshold
D0 R 0 Right AGC Saturation Flag
0: Right AGC is not saturated
1: Right AGC gain applied = maximum allowed gain for right AGC
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